1. Field of the Invention
The present invention relates to semiconductor integrated circuit devices, and more particularly, to a structure of a semiconductor integrated circuit device that can have efficient designing of an electrostatic protection circuit that protects internal elements from various types of surge generated between an input/output terminal and each power supply and between different power supplies when driven by a plurality of different power supplies.
2. Description of the Background Art
In accordance with increase in the speed of a semiconductor integrated circuit device, it has become necessary to increase the drive current of the output buffer of a semiconductor integrated circuit device.
Since the power supply potential of the power source for the output buffer circuit is apt to vary as the drive current is increased, measures must be taken to prevent erroneous operation of other internal circuits. In many cases, a power supply potential is provided to internal circuitry from a power source provided independent of the power source for the output buffer.
It is therefore necessary to achieve efficient designing of an electrostatic protection circuit corresponding to a plurality of power supplies.
FIG. 21 is a schematic diagram of a structure of a semiconductor integrated circuit device 6000 which is a semiconductor integrated circuit of the conventional master slice type gate array structure including an electrostatic protection circuit provided corresponding to a transistor group for an output buffer.
In the semiconductor integrated circuit device of FIG. 21, the output buffer formed of a group of transistors is supplied with a power supply potential for the output buffer (referred to as "Vdd1" hereinafter) and a ground potential (referred to as "Vss1" hereinafter) corresponding to Vdd1 through a Vdd1 power supply line (referred to as "Vdd1 line" hereinafter) 22 and a Vss1 power supply line (referred to as "Vss1 line" hereinafter) 23, respectively.
Electrostatic protection circuit 40 includes transistors 41 and 42.
Transistors 41 and 42 are connected between an input/output terminal 11 and Vdd1 line 22 and between input/output terminal 11 and Vss1 line 23, respectively, for the purpose employing a transistor not used in the group of transistors for the output buffer as a diode.
Transistor 41 functions as a PN diode having its gate connected to the region right under the gate (referred to as "body" hereinafter) and to either the source or drain (called "diode-connected" hereinafter) with the direction from input/output terminal 11 towards Vdd1 line 22 as the forward direction.
When a positive surge voltage that is referenced to Vdd1 line 22 is generated at input/output terminal 11, transistor 41 is turned on as a diode to remove the positive surge potential by the path from input/output terminal 11 to transistor 41 to Vdd1 line 22.
As a result, output buffer circuit 21 is protected from the positive surge voltage generated at input/output terminal 11.
Diode-connected transistor 42 functions as a PN diode with the direction from input/output terminal 11 to Vss1 line 23 as the reverse direction to protect output buffer 21 from the negative surge voltage that is referenced to Vss1 generated at input/output terminal 11.
A structure of an electrostatic protection circuit in which a plurality of internal circuits formed on the same substrate is operated by various independent power supply lines is disclosed in Japanese Patent Laying-Open No. 5-291503
FIG. 22 is a schematic diagram of an electrostatic protection circuit in a semiconductor integrated circuit device that operates by three independent power supply lines.
Referring to FIG. 22, a semiconductor integrated circuit device 7000 includes three internal circuits 301-303, and power supply lines 311-313 and ground lines 321-323 for supplying a power supply potential and a ground potential, respectively, to the above internal circuits, respectively.
Semiconductor integrated circuit device 7000 further includes diode pairs 341-346 connected between each of power supply lines 311-313 and between each of ground lines 321-323. Each diode pair (referred to as "bi-directional diode pair" hereinafter) includes two diodes connected parallel and opposite to each other. The technique of forming an electrostatic protection circuit between each of three independent power supply lines and ground lines by diode pairs 341-346 is disclosed.
In order to reduce the resistance of the electrode for the transistor included in a semiconductor integrated circuit device, the technique of covering the surface with a compound of metal and silicon called silicide is generally employed.
However, when an electrostatic protection circuit is formed by an unused diode-connected transistor as shown in FIG. 21 or 22, the resistance of the source/drain electrode of the transistor must be increased to a certain level so that the excessive current flowing through the electrostatic protection circuit will not damage the electrostatic protection circuit per se.
Thus, the silicide protection technique is employed to achieve an effect equal to that of applying resistance equivalently by providing a region where the silicide film is not formed at the electrode surface of the transistor.
When the transistor group for the output buffer has a gate array structure and driven by a plurality of independent power supply lines, the electrostatic protection circuit must be implemented to allow efficient designing of a higher degree of freedom with a smaller layout area using transistors formed of the same size.
The surge applied to the semiconductor integrated circuit device from an external source includes various types depending upon the generation status and generation source as is appreciated from the fact that various models such as HBM (Human Body Model), MM (Machine Model), CDM (Charged Device Model) and the like are considered as evaluation models.
Therefore, in the electrostatic production circuit functioning as a path to discharge the surge, the appropriate value of the resistance and the capacitance of the entire path including the parasitic parameter differs depending upon the type of the surge.
In conventional art, the region that is not silicided is designed in common to all the transistors in the application of the above-described silicide protection. This means that, even if the electrostatic production circuit is formed by connecting a plurality of transistors in parallel, the resistance value of the path to remove the surge is substantially identical. The electrostatic protection circuit may be appropriate to discharge surge of a certain type, but not appropriate for another type of surge. There was a problem that a sufficient electrostatic protection function could not be exhibited.